1. Field of the Invention
This invention relates in general to pulse generating circuits and, more particularly, to pulse generating circuits which generate a pulse train exhibiting a predetermined duty cycle.
2. Description of Related Art
Situations arise in circuit design where it is desirable to convert a pulsed signal with one duty cycle to a pulsed signal exhibiting a different predetermined duty cycle. Many circuits which are designed to expect a predetermined duty cycle as an input do not function properly if they receive an input signal exhibiting other then the predetermined duty cycle. In this situation, it is desirable to convert a pulse signal with an arbitrary duty cycle into a signal with the predetermined duty cycle. This permits circuitry which has been designed to expect the predetermined duty cycle signal as an input to properly function.
For example, one approach is to employ a phase locked loop which doubles the frequency of the input pulse signal. An edge triggered toggle flip flop can then be used to generate the converted output signal. FIG. 1A shows an arbitrary pulsed input signal which is to be converted into a 50% duty cycle output waveform. FIG. 1B shows the phase locked loop (PLL) output signal which exhibits the doubled frequency. FIG. 1C shows the toggled flip flop output signal which triggers on each leading edge of the frequency doubled PLL output signal to generate a pulsed output signal. This pulsed output signal exhibits a predetermined 50% duty cycle despite the relatively low, arbitrary duty cycle of the input pulse signal shown in FIG. 1A. This approach successfully converts the duty cycle of an input pulse signal to a 50% duty cycle, but it is not without its disadvantages. For example, the PLL circuit is a relatively complex circuit with many parameters which must be defined. This contributes to the relatively high cost of the PLL approach in view of the task to be accomplished. Moreover, this technique can exhibit stability problems. Additionally, using this approach to create a duty cycle other than 50% typically involves increasing the signal frequency to many times the input frequency thus limiting the usefulness of the PLL approach for higher frequency systems.